In a one device dynamic RAM structure, the device charge transfer efficiency of each cell of the RAM structure is inversely related to the ratio of the capacitance of the bit line to the storage capacitance of the cell. Thus, the charge transfer efficiency of the cell can be increased through decreasing the capacitance of the bit line and/or increasing the storage capacitance of the cell.
One previous arrangement for forming the bit line has been to diffuse a bit line of one conductivity into a substrate of the opposite conductivity. However, this has produced a PN junction resulting in a relatively large capacitance of the bit line.
One previously suggested means of reducing the relatively large capacitance of the bit line produced by the PN junction is to form the bit line of polycrystalline silicon as set forth in pages 3828-3831 of the February 1979 (Volume 21, No. 9) issue of the IBM Technical Disclosure Bulletin. This requires formation of contact holes to the diffused drain regions, which are to be contacted by the polycrystalline silicon bit line, prior to the polycrystalline silicon bit line being deposited. Thus, to compensate for alignment tolerances, the contact holes must be relatively large in comparison with self-aligned contacts so that there is a substantial junction area between the diffused drain regions and the bit line but the capacitance of the bit line is decreased by the use of the polycrystalline silicon bit line in comparison with the prior diffused bit lines.
While forming the bit line of polycrystalline silicon will reduce the capacitance of the bit line, it also decreases the conductivity of the bit line. Thus, forming the bit line of polycrystalline silicon instead of having a diffused bit line lowers the sheet resistance of the bit line. Therefore, a polycrystalline silicon bit line improves the charge transfer efficiency of a storage cell to some degree because of the reduction in the capacitance of the bit line in comparison with the diffused bit line but lowers the conductivity of the bit line in comparison with the diffused bit line.
One means of improving the conductivity of a polycrystalline silicon conductor line has been to utilize a metal silicide therewith. This is discussed in U.S. Pat. No. 4,180,596 to Crowder et al, pages 5466 and 5467 of the May 1980 (Volume 22, No. 12) issue of the IBM Technical Disclosure Bulletin, and page 1691 of the September 1979 (Volume 22, No. 4) issue of the IBM Technical Disclosure Bulletin. Thus, the capability of increasing the conductivity of a polycrystalline silicon conductor line through the use of a metal silicide has been previously recognized. However, none of these has self-aligned contacts.
The present invention not only produces a reduction in the capacitance of the bit line in comparison with the diffused bit line or the polycrystalline silicon bit line but also reduces the sheet resistance of the bit line. As a result, the cycle time of each of the cells is significantly reduced. Therefore, a cell of a one device dynamic RAM structure can operate faster than those utilizing polycrystalline silicon bit lines.
By reducing the capacitance of the bit lines so that the charge transfer efficiency is increased, the cells of the one device dynamic RAM structure can be made with smaller dimensions and still achieve the same performance as was previously obtained from a cell using the polycrystalline silicon bit line, for example. Accordingly, the present invention enables an increase in the density of the cells on a substrate.
In a prior method for forming a one device RAM structure, a photolithographic etching step has been employed to open contact holes in the layer of silicon dioxide to active regions of the device such as the drain region of the field effect transistor (FET), for example. This has required spaces to be reserved in the structure to compensate for the etch bias and the photolithographic mask overlay alignment tolerance.
With the method of the present invention in which self-aligned contacts are produced, the photolithographic etching step is eliminated so that the reserved spaces for the etch bias and the photolithographic mask overlay alignment tolerance are not needed. Accordingly, this allows a further reduction in the dimensions of the cells to enable a further increase in the density of the cells on a substrate.